I did my PhD on a purported successor to this - rather than using magnetic bubbles the idea was to use things called Skyrmions which emerge naturally in some materials as either information carriers or to store data in place. In practice it’s never really been taken up by industry for a few different reasons (density, can’t move the skyrmions in a straight line with a current, difficult to read whether one exists or not in a specific place).
Someone gave me a board with bubble memory chips to examine, but when I opened up the chip it turned out to be regular DRAM; they were mistaken about the type of memory.
Which bubble "chips" would someone confuse with dram? All the Intel, TI, Hitachi and Russian ones I've ever seen are relatively large, square, thick and decidedly un-DRAM like.
I have several working bubble memory boards. You can't take them apart. :-)
This was an IBM board so all the chips were in large, square, metal packages. These packages are descendants of the SLT modules used in the System/360.
Oh wow I’d never heard of bubble memory before. That’s crazy.
The (in retrospect) strange and complicated things people came up with to store bits before magnetic core got popular and then later silicon wiped the field are so much more interesting than what we’ve got now.
I get why silicon won. But it’s just nowhere near as fun as bubble memory, delay lines, or CRTs.
I know. I saw the bubble memory was used in the 70s and maybe even 80s, which is long after the days of core memory being becoming common.
And I know DRAM isn’t exactly simple.
But it just doesn’t feel as neat to me as pushing bubbles around or using a transducer to put a wave through mercury or other delay line. Or drawing a “picture of memory” for no one on a CRT because that _is_ your memory.
If one of those had won and was what everyone was used to, I’m probably think they were old hat and DRAM was crazy and cool. But that’s not how history worked out.
There is not that much complexity (circuit-wise) in the DRAM array itself apart from the fact that the sense amplifier is essentially an SRAM cell and not really an “amplifier”. Another layer of ridiculous complexity is how to interface that to the outside world without spending the precious die area of DRAM optimized process for complex interface logic or PHYs, so you get the only high-speed single ended parallel bus with weird voltage levels interface that is used in modern computers.
the dram array is pretty simple, it's true, but its behavior isn't, and the circuitry around the edges to make it act like ram isn't. you have the sense amplifiers with their inputs that are also their outputs, yeah, but also precharge, refresh, and stuff i'm not privy to
